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r2000

The R2000 is a microprocessor chip set developed by MIPS Computer Systems that implemented the MIPS I instruction set architecture. Introduced in January 1986, it was the first commercial implementation of the MIPS architecture and the first merchant RISC processor available to all companies. The R2000 competed with Digital Equipment Corporation VAX minicomputers and with Motorola 68000 and Intel Corporation 80386 microprocessors. R2000 users included Ardent Computer, DEC, Silicon Graphics, and MIPS's own Unix workstations. The chip set consisted of the R2000 microprocessor, R2010 floating-point accelerator, and four R2020 write buffer chips. The core R2000 chip executed all non-floating-point instructions with a simple short pipeline. This chip also controlled the external code and data caches, made of fast standard SRAM chips organized with direct indexing and one-cycle read latency. The R2000 chip contained a small translation lookaside buffer for mapping virtual memory addresses. The R2010 chip held the floating point registers, floating point data paths, and their longer simple pipeline. Writes to main memory DRAM took tens of cycles to fully complete. But the R2020 chips queued and completed up to 4 pending writes to main memory, allowing the R2000 core to proceed without stalling itself. In the absence of cache misses, this chip set sustained an instruction completion rate of one instruction per ALU cycle. This was much faster than non-RISC microprocessors of that time which needed several cycles per instruction. 1986 also saw similar technology in Sun's first SPARC microprocessor and Hewlett Packard's first PA-RISC microprocessor.²

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